The present invention relates to a fin field effect transistor (finFET), and more specifically, to the integrated formation of silicon (Si) and silicon germanium (SiGe) fins.
As integrated circuits continue to scale downward in size, the fin field effect transistor (finFET) is used increasingly with advanced technology nodes (e.g., the 22 nanometer (nm) node and beyond). In a finFET, the channel is formed by a semiconductor fin, and a gate electrode is located on at least two sides of the fin. Due to the advantageous feature of full depletion in a finFET (current between source and drain flows only through fins), the increased number of sides on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET compared to a planar MOSFET. The improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. In finFET devices, the conducting channel is wrapped by a Si or SiGe fin. The thickness of the fin (in the direction from source to drain) determines the channel length of the device. A complementary metal-oxide semiconductor (CMOS) device includes an Si fin in the n-channel FET (nFET) region and a SiGe fin in the p-channel FET (pFET) region. Thus, the Si and SiGe fins must be integrated on the same wafer. Currently, a silicon well is formed to define the pFET region, and advanced patterning techniques are used to pattern the SiGe fin.